1. Field of the Invention
The present invention relates to an AGC circuit that, in a communication system or audio system, controls the gain of a variable gain amplifier circuit in accordance with the amplitude of input signal so that the amplitude of output signal is kept at a specific level and thereby restricts the fluctuation in the input signal.
2. Description of the Related Art
As a related art of the AGC circuit, a proposal is disclosed in Japanese Patent No. 2901899.
FIG. 17 shows the AGC circuit according to the related art set forth in the above Japanese Patent No. 2901899. In FIG. 17, reference numeral A1 denotes a signal input terminal to which an input signal VA is supplied. Reference numeral 31 denotes a variable gain amplifier circuit that amplifies or attenuates the input signal VA in accordance with the gain, which is controlled by a gain control voltage V33, and outputs an output signal VB. Reference numeral B1 denotes an output terminal of the variable gain amplifier circuit 31.
Reference numeral 32 denotes a rectification circuit that rectifies an output voltage of the variable gain amplifier circuit 31. Reference numeral 33 denotes a signal integration circuit that integrates the voltage rectified by the rectification circuit 32 into a D.C. voltage. Reference numeral 34 denotes a resistor constituting the signal integration circuit 33. Reference numeral 35 denotes a capacitor constituting the signal integration circuit 33.
Reference numeral 36 denotes a D.C. amplifier circuit that outputs a voltage proportional to a difference between the D.C. voltage V31, which is input from the signal integration circuit 33, and a reference voltage V32 as again control voltage V33. Reference numeral 37 denotes a reference voltage input terminal of the D.C. amplifier circuit 36. The gain control voltage V33 controls the gain of the variable gain amplifier circuit 31, which is an output voltage of the D.C. amplifier circuit 36.
In FIG. 17, a reference voltage circuit and a voltage control switch of the D.C. amplifier circuit 36 and a circuit, which switches the AGC circuit between ON and OFF, are omitted.
Reference voltage to be given to the D.C. amplifier circuit 36 is generated by a resistance-dividing network. A MOS transistor is connected to the output section of the resistance-dividing network. The AGC characteristics are changed by ON/OFF operation of the MOS transistor to change the value of the reference voltage. The MOS transistor is call as voltage control switch.
The operation of the above-described AGC circuit according to the related art, will be described below with reference to the drawing.
The input signal VA, which is input from the input terminal A1, is amplified or attenuated by the variable gain amplifier circuit 31 and output from the output terminal B1 as the output signal VB. The output signal VB is converted into the D.C. voltage V31 corresponding to the magnitude (amplitude) thereof by the rectification circuit 32 and the signal integration circuit 33. The D.C. voltage V31 is further input into the D.C. amplifier circuit 36.
The D.C. amplifier circuit 36 outputs a voltage proportional to the difference between the D.C. voltage V31 and the reference voltage V32 as the gain control voltage V33. The gain control voltage V33 is given to the variable gain amplifier circuit 31.
The AGC circuit is adapted so that, when the amplitude of the input signal VA is large, the gain of the variable gain amplifier circuit 31 is lowered; when the amplitude of the input signal VA is small, the gain of the variable gain amplifier circuit 31 is raised. Accordingly, by repeating the above operation, the output signal VB is converged into a specific amplitude level. The level can be previously determined from the relationship among the D.C. voltage V31, the reference voltage V32 and the gain control signal voltage V33 or the gain of the variable gain amplifier circuit 31.
According to the related art, the response time of the AGC, i.e., the attack time and the recovery time is determined by selecting the capacitance value of an external capacitor. For example, when the capacitance value of the external capacitor is 0.47 μF, the attack time is approximately 1 msec; and the recovery time is approximately 1 sec.
However, in the related art of the AGC circuit, it is necessary to convert the output signal VB of the variable gain amplifier circuit 31 into the D.C. voltage V31 by integrating the rectified signal which has been rectified by the rectification circuit 32.
However, to achieve the above, a time constant for the integration operation, which depends on the resistance value of the resistor 34 and the capacitance value of the capacitor 35 constituting the signal integration circuit 33, has to be set to be large enough with respect to the minimum frequency of the analog signal as the input signal VA. As a result, there resides such problem that, generally, the capacitance value of the capacitor 35 becomes an extremely large value, which is impossible to be integrated within a semiconductor integrated circuit.